1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor liquid crystal display(TFT-LCD), and more particularly, to a method of fabricating a thin film transistor liquid crystal display with repair circuit.
2. Description of the Prior Art
Due to continued development and advancement in electrical technology, the variety of applications as well as the demand for liquid crystal displays is ever increasing. A liquid crystal display(LCD) is one type of flat panel display and is employed extensively in applications ranging from small-scale products, such as a phygmomanometer, to various portable electronic devices such as PDAs and notebooks, and even to the commercial large panel displays. Since an LCD has the advantages of lightweight, low energy consumption, and free of radiation emission, the LCD is extensively applied to informational products and has a great potential for the future. Basically, the conventional TFT-LCD includes a transparent substrate having a matrix of thin film transistors, pixel electrodes, scan lines, signal lines orthogonal to the scan lines, a color filter, and liquid-crystal materials between the transparent substrate and the color filter. With the supporting electrical devices, such as capacitors and bonding pads, the TFT-LCD device drives liquid-crystal-pixels to generate color-rich graphics. However, when fabricating the TFT-LCD, point defects or line defects readily occur on the crossover region of a scan line and a signal line and on the thin film transistor due to human error and processing factors.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a top view of a single TFT-LCD device 10 according to a prior art. FIGS. 2A-2E are cross-sectional diagrams of fabricating a thin film transistor and a crossover region of a scan line and a signal line of the TFT-LCD device 10 shown in FIG. 1 according to the prior art. The prior art technology utilizes photo-etching-processes (PEP) five times to form the TFT-LCD device 10 on a transparent glass substrate 11. The substrate may be a quartz substrate or a plastic substrate.
When fabricating the LCD panel, various devices including a thin film transistor, a pixel electrode, a scan line, a signal line, a capacitor, and a bonding pad are formed on the panel. Since each device is disposed according to a special layout and has a specific special relationship with the other devices, it is too complicated to show all of them in a cross-sectional diagram and a top view diagram. Therefore, only the thin film transistor 44, the pixel electrode 42, the scan line 18, the signal line 36, and a crossover region 14 of the scan line 18 and the signal line 36 are shown in FIG. 1 and FIG. 2.
Referring to FIG. 1 and FIG. 2, the glass substrate 11 (not shown in FIG. 1) comprises at least one thin film transistor(TFT) 44, the scan line 18, and the signal line 36.The thin film transistor 44 is disposed in the transistor region 12 on the glass substrate 11. The scan line 18 and the signal line 36 orthogonal to the scan line 18, cross in the crossover region 14 on the glass substrate 11. A source electrode 32 of the thin film transistor 44 is connected to the signal line 36, and a drain electrode 34 of the thin film transistor 44 is connected to a pixel electrode 42 through a via hole 41. An etching stop pattern 26 is disposed on a gate electrode 16.
In the prior art method, a first metal layer(not shown) is deposited on the surface of the glass substrate 11, then a first photo-etching-process(PEP-1) is performed to form the gate electrode 16 and the scan line 18 passing through the crossover region 14 on the surface of the glass substrate 11, as shown in FIG. 2A. The gate electrode 16 is connected to the scan line 18. The first metal layer (not shown) is a single-layered metal or a double-layered metal. In the previous case, the first metal layer (not shown) is composed of tungsten (W), chrome (Cr), molybdenum (Mo) or the molybdenum-tungsten (MoW) alloy. In the latter case, the first metal layer (not shown) is composed of chrome (Cr) on top of aluminum (Al), molybdenum (Mo) on top of aluminum, molybdenum on top of aluminum-neodynium (AlNd) alloy, molybdenum-tungsten (MoW) alloy on top of aluminum, or molybdenum-tungsten (MoW) alloy on top of aluminum-neodynium (AlNd) alloy. The above-mentioned material compositions of the double-layered metal are examples frequently seen. Actually, the material compositions of the double-layered metal could be the random combination of chrome (Cr), aluminum (Al), molybdenum (Mo), the aluminum-neodynium (AlNd) alloy, and the molybdenum-tungsten (MoW) alloy.
After the PEP-1, a gate insulator layer 22 and a semiconductor layer 24 are deposited on the glass substrate 11. The gate insulator layer 22, composed of silicon oxide (SiOx), silicon nitride (SiNy), or silicon oxynitride (SiOxNy), may be a single dielectric layer or a composite dielectric layer. The semiconductor layer 24, also called as an active layer, is a hydrogenated amorphous silicon layer (xcex1-Si:H layer), and is used as a channel when the thin film transistor 44 is turning on. The semiconductor layer 24 could be a polysilicon layer.
Then, an etching stop layer (not shown), composed of silicon nitride, is formed on the glass substrate 11. Actually, the gate insulator layer 22, the semiconductor layer 24, and the etching stop layer (not shown) are formed in the same chamber during a continuous plasma enhanced chemical vapor deposition (PECVD) process. A second photo-etching-process(PEP-2) is thereafter performed to form an etching stop pattern 26 above the gate electrode 16 to prevent the semiconductor layer 24 from damaging in subsequent etching process. In the crossover region 14, the etching stop layer (not shown) is not retained at all, as is shown in FIG. 2B.
As shown in FIG. 2C, a doped semiconductor layer (n+ layer, not shown) is deposited on the semiconductor layer 24 and the etching stop pattern 26. The doped semiconductor layer (not shown) is usually composed of amorphous silicon doped with phosphor. After that, a second metal layer (not shown) is deposited on the doped semiconductor layer (not shown). A third photo-etching-process(PEP-3) is then performed to pattern the second metal layer (not shown), the doped semiconductor layer (not shown) and the semiconductor layer 24 for forming the source electrode 32, the drain electrode 34 and the active area (not shown) of the thin film transistor in the transistor region 12, and a signal line 36 passing through the crossover region 14 simultaneously.
The second metal layer (not shown) is a single-layered metal or a multi-layered metal. In the previous case, the second metal layer (not shown) is composed of tungsten (W), chrome (Cr) or Molybdenum (Mo). In the latter case, the second metal layer (not shown) is composed of chrome (Cr) on top of aluminum (Al), molybdenum (Mo) on top of aluminum, molybdenum on top of aluminum-neodynium (AlNd) alloy, molybdenum-tungsten (MoW) alloy on top of aluminum, or molybdenum-tungsten (MoW) alloy on top of aluminum-neodynium (AlNd) alloy or sandwich structure as molybdenum/aluminum/molybdenum (Mo/Al/Mo) or molybdenum/aluminum-neodynium/molybdenum (Mo/AlNd/Mo). The above-mentioned material compositions of the multi-layered metal are examples frequently seen. Actually, the material compositions of the multi-layered metal could be the random combination of chrome (Cr), aluminum (Al), molybdenum (Mo), the aluminum-neodynium (AlNd) alloy, and molybdenum-tungsten (MoW) alloy. The doped semiconductor layer (not shown) is used to improve the ohmic contact of the second metal layer (not shown) to the semiconductor layer 24 to avoid the contacting problems between the second metal layer (not shown) and the semiconductor layer 24.
A passivation layer 38, composed of silicon oxide or silicon nitride, is thereafter formed on the glass substrate 11. After that, a fourth photo-etching-process(PEP-4) is performed to remove portions of the passivation layer 38 atop the drain electrode 34 of the thin film transistor 44 so as to form a via hole 41 in the passivation layer 38. The via hole 41 extends from the top surface of the passivation layer 38 up to the top surface of the drain electrode 34 to expose portions of the drain electrode 34 as is shown in FIG. 2D, or extends from the top surface of the passivation layer 38 up to the top surface of the first metal electrode in the peripheral area of the panel for contacting with the common electrode of color filter in subsequent process (not shown).
Finally, a transparent conductive layer(not shownO, composed of indium tin oxide (ITO) or indium zinc oxide (IZO), is formed on glass substrate 11. Then, a fifth photo-etching-process(PEP-5) is performed for forming a pixel electrode 42 electrically connected to the drain electrode 34 of the thin film transistor 44 via via hole 41 so as to complete the fabrication of the thin film transistor 44. At this point, as shown in FIG. 2E, only the doped semiconductor layer (not shown), semiconductor layer 24 and the gate insulator layer 22 are positioned between the signal line 36 and the scan line 18 in the crossover region 14 covered by the passivation layer 38.
In summary, the prior art method of fabricating a thin film transistor liquid crystal display does not provide any repair circuit. However, the yield of the thin film transistor liquid crystal display is readily affected due to various defects occurring after repeated processing. This problem tends to be more and more serious as the size of the liquid crystal display becomes larger, especially at the crossover region 14, where the signal line 36 and the scan line 18 pass through at the same time, and around the transistor region 22. Because the taper shape of the scan line 18 or the gate electrode 16 at a lower level is not good, the under cut phenomena of the scan line 18 or the gate line exists, the metal eruption phenomenon occurs, and unexpected particles are generated in the semiconductor layer 24 and the gate insulator layer 22, the gate-signal short phenomenon thus occurs after depositing the second metal layer.
Therefore, it is very important to design and make a repair circuit in the thin film transistor, so a laser repair process is performed to ensure a certain production yield after the TFT-LCD device 10 with gate-signal short phenomenon is detected by an array test.
It is therefore an object of the claimed invention to provide a method of fabricating a thin film transistor liquid crystal display(TFT-LCD), especially a method of fabricating a thin film transistor liquid crystal display with a laser repair circuit to perform a laser repair process easily.
According to the claimed invention, a substrate is provided first. At least one transistor region for forming a thin film transistor (TFT) and at least one crossover region are on the substrate. A first metal layer is formed on the substrate, then the first metal layer is patterned by removing a part of the first metal layer to form a gate electrode in the transistor area,a scan line passing through the crossover region,and a first repair pad at either side of the crossover region simultaneously on the substrate. Thereafter a dielectric layer and a semiconductor layer are sequentially deposited on the substrate to cover the gate electrode, the scan line, and each first repair pad. After that, an etching stop layer is formed on the semiconductor layer above the gate electrode. A doped semiconductor layer is formed on the semiconductor layer and the etching stop layer. A second metal layer is formed on the doped semiconductor layer. Then the second metal layer, the doped semiconductor layer and the semiconductor layer are patterned by removing a part of the second metal layer, the doped semicondutor layer and the semiconductor layer to form a source electrode and a drain electrode and to define the active area of the thin film transistor in the transistor region and to form a signal line passing through the crossover region simultaneously. A passivation layer is thereafter formed on the substrate. After that, the passivation layer is patterned by removing a part of the passivation layer positioned above the drain electrode to form a via hole extending to the top surface of the drain electrode or extending to the first metal electrode in the peripheral area of the panel for contacting with the common electrode of color filter in subsequent process.
Then a transparent conductive layer is formed on the substrate and the transparent conductive layer fills up the via hole. Finally, the transparent conductive layer is patterned by removing a part of the transparent conductive layer, to form a pixel electrode electrically connected to the drain electrode via the via hole on the substrate and simultaneously form a second repair pad above each first repair pad. Each first repair pad and the second repair pad form a repair circuit region.
The method of fabricating the TFT-LCD device according to the claimed invention is to add a repair circuit into the layout, to simultaneously fabricate a bottom repair pad, connected to the scan line, at either side of the crossover region when forming the scan line, and to retain the transparent conductive layer atop the bottom repair pad when etching the transparent conductive layer. When performing the repair process, a laser repair process includes the steps of cutting off the scan line, punching through the passivation layer and the gate insulator layer, and laser welding the top repair pad is performed to the gate-signal short portion. The repair process is thus very easily performed to ensure a certain production yield without adding extra process steps.